C to Verilog

You may use most of the C language features except for a limited list of features including recursive functions, structs, pointers to functions and library function calls (printf, malloc, etc). These cannot be represented in hardware. You MAY define multiple functions as long as you declare them as 'static inline'. You MAY use any of the standard types (array, pointers, int) but may NOT use float/double types. You may not declare global variables and arrays which are local to the function. All of your arrays must be declared as parameters of your function. Only one-dimensional arrays are supported.
You can find more code samples in the Examples page.
The code below is fine:

unsigned int fib(unsigned int A[], unsigned int n) {
  
      unsigned int last, prelast, curr;
      prelast = 0;
      last = 1;
      unsigned int i;
      for (i = 2; i < n; i++) {
          curr = prelast + last;
          prelast = last;
          last = curr;
          A[i] = curr;
      }
      return curr;
  }

Yes. If you are interested in synthesizing your code without submitting your intellectual property over the internet then you can install the C-to-Verilog evaluation version in your local workstation. Download the source code from the Research page. You will need LLVM 2.5;
Please contact us for more information.

The interface for your hardware module is defined by your C code. By default every generated module has Clock and Reset inputs. In addition the generated module has ReturnValue and Ready outputs to indicate the return value of the function and to signal when the operation is completed.
For any other integer parameter the synthesis will generate an input parameter. For any pointer in your function parameter list, the synthesis will generate a block-ram port. You will be able to connect each array parameter to an external block-ram port. The memory ports have the standard input, output, address and write-enable signals.

This chart below explains the relationship between the argument list and the generated module. Notice how the two array parameters became two memory ports. In addition to the standard memory port entries there is a base parameter. This parameter is the offset of the array inside the block-ram.

When c-to-verilog generates your code, it also generates an automatic testbench. It assigns empty block-rams to each of your array parameters and default values to your integers. It will even try to detect loop index parameters and assign them non-zero values. After creating the module, you simply need to edit the parameters you would put into your C program. Each C parameter becomes a verilog parameter. Each pointer becomes one or more memory ports. The ports are already connected in the testbench (see memory
configuration). Also, in addition to the memory port, each array has a 'base address' parameter so you can configure (in RTL) where your array starts within the Block-Ram on the FPGA.
You can use ModelSim or any of the other commercial software.
Alternatively, can use the Icarus verilog simulator to execute the generated testbench. See example below.

#To compile the verilog module use:
iverilog my_module.v -o my_bench
#And to execute the generated module:
./my_bench

On FPGAs the number of LUTs and flip-flops is limited. Our compiler optimizes size, area and performance. However, in some cases the user may decide to use different trade-offs. The ALU units parameter will decide how many multipliers, adders, dividers and shifters will be assigned to your design. The more ALUs are assigned the faster (and also bigger) your design will be. The size of each ALU depends on your FPGA. For example, Virtex4 FPGAs have built-in multipliers (called DSPs) and therefor more ALUs will require more 'DSPs' but not much more LUTs.
In the near future we will allow modifications/selection of other different parameters.

We optimize some of the synthesizes parameters according to the target FPGA. For example, some FPGAS have 6-input LUT arcitecture while others have 4-input. Some FPGAs have built-in DSP (ASIC multipliers) while others have better MUX units. We take some of these parameters into account. We consider the following FPGAs:
Virtex4, Virtex5 and Spartan3 by Xilinx.
Stratix, Cyclone by Altera.
However, your designs should work on ASICs and other FPGA vendors.

At this point C-to-Verilog cannot generate VHDL. We do plan to add VHDL support in the future. If this feature is important to you, please send us an email and we will see what we can do.

Yes, of course. We implement Modulo Scheduling, which is an excellent technique for exposing parralelism. We also implement resource reuse, arithmetic operation overlapping and other optimizations.
You can help the system to create a better pipeline by following a few simple rules. First, in the body of a loop, do not read and write from the same array. Reading and writing from the same array inside the body of a single loop may create logical dependencies which hinder parallelism. Beside that, the tool does a pretty good job on its own.

for (int i=0; i<N; i++) {
// This code will be pipelined on the FPGA
A[i] = B[i]; // GREAT, no dependencies between cells
}

for (int i=0; i<N; i++) {
//NOT IDEAL, this will not be pipelined and will span multiple cycles.
A[i] = A[i+1]; 
}

The pop-count Howto is a good example for the advantages of a pipeline verilog hardware design.

We do a pretty good job. However, most good circuit designers will be able to look at the problem and after a few days create a design which is equivalent or better than what we can do. Humans are free to think, try different approaches, and change the algorithm. Software is limited to the explisit and implicit requests of the user.

We are not the only software out there that synthesizes C-to-RTL. However, most of the commercial products out there do not perform real optimizations. A C to RTL synthesizer is only worth considering if it schedules, pipelines, reuses and optimizes the code. (WE DO!)
The two or three leading products all implement the same pipelining algorithms (See pipelining). Some have nicer IDEs and pretty buttons.

Nothing. Unless you send us an email to report a problem. See our Privacy statement.

C-to-Verilog.com respects your privacy. You do not need to register or confirm your email address to use our service. If you give us your real email and our servers are busy, we will schedule your synthesis to run over night and send you the result later on.
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email: info@c-to-verilog.com

You need to add the new Verilog module to your embedded design manually.
If you are using Xilinx EDK you can use the "Create and Import Peripheral" wizard. You will need to write some VHDL/Verilog glue code.

When designing a hardware circuit for an FPGA, you often use Block-Rams. In your design you may decide to connect memory arrays with different parameters. First, you can decide to connect an array of words where the size of word is 8 bits, 16 bits or 32 bits. This parameter can be configured by the "Array word size" in the hardware configureation menu. This parameter will only affect the testbench. In your output verilog module, the width of each IO memory port will be decided by the type of the pointer. For example, a pointer to "char A[]" will create an interface to an array with 8-bit element. A "int B[]" will create an interface to a 32-bit one. If you configure an "Array word size" which is bigger than what you need then a part of the word will be trimmed. Keep in mind that this is only the testbench. When you intergrate the module into your design you can assign the needed Block-Ram size.
Secondly, you may decide that the size of your array will contain many elememts and require a large address word bitwidth, or you may decide that it will be small and only require a small address bitwidth. The parameter "Address bitwidth" will configure the address width within your design.
The Hadamard/Walsh Transform is a good example of where we benefit from multiple memory ports.

C-to-Verilog designs should work on all FPGA boards as well as ASIC. If you are new to FPGA development Digilent is a good place to start. They provide inexpensive Xilinx design kits.

Embedded systems are dominated by extensive loop processing and low power budget. In many cases these loops can be compiled to hardware circuits that are significantly faster and more power efficient compared to their software versions. Efficiently compiling from high-level languages, such as C, to gate-level may reduce time-to-market, ease verification, and lower the design costs. Such a tool must achieve good performance in terms of design size, execution time, and power consumption. These restrictions are the fundamental problems in high level synthesis (HLS).

The CHStone benchmark suite is a collection of programs from various domains, some of which originally belong to other benchmark suites. CHStone can be used to test High-Level Synthesis tools.