About C-to-Verilog

C-to-Verilog.com is the result of an academic study in the field of high-level synthesis at Haifa University. The compiler used in C-to-Verilog.com is a modified version of the SystemRacer synthesis system. The source code of the compiler is available for research purposes and has been given to a number of compiler groups around the world. The publications below describe the implementation of the synthesis system. Please cite these publications when refering to this website.

The source code to the system is available in this link. The code is licensed under the GPL3 License. The synthesis system requires integration with LLVM 2.5 as a backend target.

  1. Synthesis for Variable Pipelined Function units
    Nadav Rotem, Yosi Ben Asher
    SOC 2008, Tampere, Finland, November 2008.

  2. Binary Synthesis with Multiple Memory Banks Targeting Array References
    Nadav Rotem, Yosi Ben Asher
    FPL 2009, Prague, Czech Republic, August 2009.

  3. Finding the Best Compromise in Compiling Compound Loops to Verilog
    Eddie Shochat, Nadav Rotem, Yosi Ben Asher
    Journal of Systems Architecture, September 2010.

  4. Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs
    Nadav Rotem, Yosi Ben Asher, Danny Meisler
    ACM Transactions on Reconfigurable Technology and Systems, September 2010.

  5. Automatic Memory Partitioning: Increasing Memory Parallelism via Data Structure Partitioning
    Nadav Rotem, Yosi Ben Asher
    CODES+ISSS, Arizona, USA, October 2010.