C-to-Verilog.com is the result of an academic study in the field of high-level synthesis at Haifa University. The compiler used in C-to-Verilog.com is a modified version of the SystemRacer synthesis system. The source code of the compiler is available for research purposes and has been given to a number of compiler groups around the world. The publications below describe the implementation of the synthesis system. Please cite these publications when refering to this website.

1. Synthesis for Variable Pipelined Function units
   Nadav Rotem, Yosi Ben Asher
   SOC 2008, Tampere, Finland, November 2008.
   


2. Binary Synthesis with Multiple Memory Banks Targeting Array References
   Nadav Rotem, Yosi Ben Asher
   FPL 2009, Prague, Czech Republic, August 2009.
   



3. Finding the Best Compromise in Compiling Compound Loops to Verilog
   Eddie Shochat, Nadav Rotem, Yosi Ben Asher
   Journal of Systems Architecture, September 2010.

4. Automatic Memory Partitioning: Increasing Memory Parallelism via Data Structure Partitioning
   Nadav Rotem, Yosi Ben Asher
   Accepted for publication in CODES+ISSS 2010.